By now, many processors operating in the single instruction, multiple data stream (SIMD) style or the multiple instruction stream, multiple data stream (MIMD) style have been proposed. While processor of the first mentioned style, whose architecture has been disclosed in Reference 1, are mostly used for processing computationally expensive, data independent low-level tasks with regular data and control flow or medium-level tasks with their regular data access but irregular data and control flow, processor of the second mentioned style, whose architecture has been disclosed in Reference 2, work on irregular input data with irregular data and control flow. This results in the problem that the SIMD processors are wasting unoccupyable processing elements (PEs) in tasks with irregular input data, while the MIMD processors are wasting unoccupyable logic in tasks with regular input data.
Many upcoming algorithms, like for example H.264, are made up of a number of sub algorithms which follow partly the SIMD control style and partly the MIMD control style. Therefore, new dual mode SIMD/MIMD architectures have been proposed, which are mainly starting from an MIMD approach and attaching an additional crossbar to enable SIMD functionality. Examples are References 3 to 6. Other approaches have a fixed percentage of SIMD and MIMD processing power by either adding each fixed number of SIMD units and MIMD units, like in Reference 7, or by adding to an array of processing elements without memory control ability a number of so called user computers with memory control capability as suggested in Reference 8.
The references are listed below.    [Reference 1] R. A. Stokes et al., “Parallel operating array computer”, U.S. Pat. No. 3,537,074, Oct. 27, 1970    [Reference 2] A. Rosman, “MIMD instruction flow computer architecture”, U.S. Pat. No. 4,837,676, Jun. 6, 1989    [Reference 3] R. J. Gove et al., “Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation”, U.S. Pat. No. 5,212,777, May 18, 1993    [Reference 4] N. K. Ing-Simmons et al., “Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode”, U.S. Pat. No. 5,239,654, Aug. 24, 1993    [Reference 5] R. J. Gove et al., “Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors”, U.S. Pat. No. 5,522,083, May 28, 1996    [Reference 6] J. A. Sgro et al., “Scalable multi-processor architecture for SIMD and MIMD operations”, U.S. Pat. No. 5,903,771, May 11, 1999    [Reference 7] T. Kan, “Parallel data processing system combining a SIMD unit with a MIMD unit and sharing a common bus, memory, and system controller”, U.S. Pat. No. 5,355,508, Oct. 11, 1994    [Reference 8] J. H. Jackson et al., “MIMD arrangement of SIMD machines”, U.S. Pat. No. 6,487,651, Nov. 26, 2002